1. Technical Field
The present invention relates to a system for data processing in general and, in particular, to a symmetric multiprocessor data-processing system. Still more particularly, the present invention relates to a scalable symmetric multiprocessor data-processing system.
2. Description of the Prior Art
A typical symmetric multiprocessor (SMP) data-processing system has several processing units; and all of these processing units are generally identical. In other words, all the processing units have the same architecture and utilize a common set or subset of instructions and protocols to operate. Furthermore, each processing unit includes a processor core having at least one execution unit for carrying out program instructions. In addition, each processing unit may include at least one level of caches, commonly referred to as L1 or primary caches, which are implemented with high-speed memories. In most cases, a second level of caches, commonly referred to as L2 or secondary caches, may be included in each processing unit for supporting the first level caches. In some cases, a third level of caches, commonly referred to as L3 or tertiary caches, may also be included in each processing unit for supporting the second level caches. Each level of cache stores a subset of the data and instructions contained in a system memory for low latency access by the processor cores.
Despite various advantages, the scalability of a typical SMP data-processing system tends to be limited and the size of the typical SMP data-processing system is also intrinsically defined. However, in today's computing world, it is imperial to have an expandable data-processing system that can meet all the ever-growing computing demands. Consequently, it would be desirable to provide an improved SMP data-processing system architecture such that the entire system is truly scalable.